![]() This fabrication process is ready for mass production, according to Intel, though it will be deployed for the HVM of Meteor Lake's compute chiplet only several months from now. Similar to high-speed logic, ultra-low leakage transistors are often larger as well.Meteor Lake's compute tile is arguably the most exciting part of the package because it will be made on Intel 4 (previously known as 7nm), the company's first production node that will use extreme ultraviolet (EUV) lithography. In contrast, lower-speed logic like an explicitly parallel GPU or ASICs often employ the densest transistors that use just a single fin, sacrificing clock speed to improve density. In modern FinFET-based designs, this translates into more transistors with 2 fins, 3 fins, or even more. High-speed designs like the server processor tend to use more custom circuit design and larger transistors that have greater drive strength and reduced variability. The server design team will therefore optimize for frequency. For example, the Xeon 82 are both 24-core parts and the main difference is the base frequency (2.9GHz and 2.4GHz), which translates into about $1,600 difference in list price. In contrast, a faster server chip can usually command higher prices and therefore will always benefit from any incremental frequency. ![]() As a result, most ASIC design teams will tend to optimize for minimum cost with highly automated design tools, fewer custom circuits, and dense transistors. ![]() For example, the Cisco Silicon One is intended for high-speed networking using 400Gbps Ethernet and there is no advantage from boosting the frequency by 10% 400Gbps is the standard set by IEEE, and the next step after that is 800Gbps. Comparing substantially different designs such as a fixed-performance ASIC (e.g., Broadcom’s Tomahawk 4 25.6Tb/s switch chip or Cisco’s Silicon One 10.8Tb/s router chip) and a high-performance datacenter processor (e.g., Intel Cascade Lake or Google’s TPU3) is misleading at best.Īn ASIC needs to deliver the targeted throughput, but does not benefit from any incremental frequency. The transistor density is intimately related to the overall objectives and design style. Product Objectives Influence Design Style The net result is that transistor count and density are only approximate metrics and focusing on those particular numbers risks losing sight of the bigger picture. Worse yet, there is no standard way of counting transistors and the numbers can vary by 33-37% for the same design. In reality, transistor density varies considerably based on the type of chip and especially the type of circuitry within the chip. But from a customer standpoint, Moore’s Law is really a promise that the processors of tomorrow will be even better and more valuable than the processors of today. ![]() Moore’s Law in its original form observes that the transistor count of an economically optimal (i.e., minimum cost per transistors) design doubles every two years. For this reason, transistor count is often considered a proxy for the health of Moore’s Law, although that is not quite fully accurate. As the industry moves to newer process technologies, the number of transistors per unit area keeps on rising. As a recent example, when Apple released the A13 Bionic inside the iPhone 11 generation, the company crowed that it contains 8.5 billion transistors, and in 2006, Intel similarly bragged about Montecito, the first billion-transistor processor.įor the most part, these constantly increasing transistor counts are a consequence of Moore’s Law and the drive to ever greater levels of miniaturization. Upon the release of a new processor or SoC, many a vendor brags about the complexity of their design, as measured by transistor count. In the tech industry, transistor count and transistor density are often portrayed as technical achievements and milestones.
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